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93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.4
Erase
The DO pin indicates the Ready/ Busy status of the
The ERASE instruction forces all data bits of the
specified address to the logical ‘ 1 ’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
device if CS is brought high after a minimum of 250 ns
low (T CSL ). DO at logical ‘ 0 ’ indicates that programming
is still in progress. DO at logical ‘ 1 ’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/ Busy status from DO.
FIGURE 2-1:
ERASE TIMING
T CSL
CS
CLK
Check Status
DI
1
1
1
A N
A N -1 A N -2
???
A0
T SV
T CZ
DO
High-Z
Busy
Ready
High-Z
T WC
2.5
Erase All (ERAL)
The DO pin indicates the Ready/ Busy status of the
The Erase All ( ERAL ) instruction will erase the entire
memory array to the logical ‘ 1 ’ state. The ERAL cycle
device, if CS is brought high after a minimum of 250 ns
low (T CSL ).
is identical to the erase cycle, except for the different
Note:
After the ERAL command is complete,
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
issuing a Start bit and then taking CS low
will clear the Ready/ Busy status from DO.
V CC must be ? 4.5V for proper operation of ERAL.
FIGURE 2-2:
ERAL TIMING
T CSL
CS
CLK
Check Status
DI
1
0
0
1
0
x
???
x
T SV
T CZ
DO
High-Z
Busy
Ready
High-Z
T EC
DS21796M-page 6
? 2003-2012 Microchip Technology Inc.
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